1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a fabricating method of a DRAM (dynamic random access memory) capacitor. In this fabricating method, a native oxide layer is removed to lower a contact resistance of a node and the node junction fully surrounds the node to lower the junction current leakage.
2. Description of the Related Art
DRAM is a widely used IC device, and more particularly it plays an important role in the present technology. FIG. 1 shows a schematic drawing of a DRAM cell. The memory cell includes a transfer transistor T and a storage capacitor C. The source region of the transfer transistor T is connected to a corresponding bit line BL, the drain region of the transistor T is connected to a storage electrode 10 of a the storage capacitor C, and the gate is connected to a corresponding word line WL. An opposing electrode 12 of the storage capacitor C is connected to a constant voltage source region V.sub.CP. Between the storage electrode 10 and the opposing electrode 12, there is a dielectric layer 11. As practitioners skilled in the art know, the storage capacitor C should be large enough to protect the storage data from loss.
FIGS. 2A-2H are cross-sectional views showing a conventional process of fabricating a DRAM capacitor.
Referring to FIG. 2A, a substrate 20 is provided on which an isolation region 21 is formed to define a device region. The isolation region 21 is, for example, a shallow trench isolation region or a field oxide region.
Then, a transistor is formed on the device region, wherein the transistor includes a gate electrode 22, a drain region 24a, a source region 24b, and a gate oxide layer 23 which is under the gate electrode 22. The gate electrode 22 is a doped polysilicon which is formed by depositing a polysilicon layer using CVD (chemical vapor deposition), and the polysilicon layer is further implanted with dopant. Then, lightly doped regions, for example, drain regions 24a and source region 24b, are formed. Next, spacers 25 are formed on the sides of the gate electrode 22, wherein the spacers are silicon nitride. Finally, the source region 24b is further implanted to form a heavily doped region.
Referring to FIG. 2B, an oxide layer 26 is formed over the substrate 20. Then, the oxide layer 26 is defined by forming a photoresist layer. For example, the oxide layer 26 is etched by dry etching to form a contact window 28 and expose the source region 24b. After the contact window 28 is formed, the photoresist layer is removed.
Referring to FIG. 2C, a doped polysilicon layer (not shown) is deposited in the contact window 28 and on the oxide layer 26 by CVD, wherein the polysilicon layer is connected to the source region 24b. Then the doped polysilicon layer is defined, by conventional lithography technology, to form a bit line 30.
Referring to FIG. 2D, an oxide layer 32 deposited over the substrate to cover the bit line 30 and the oxide layer 26 by APCVD. Next, an oxide layer 34 is formed over the oxide layer 32 by PECVD, wherein the oxide layer 34 is BPSG.
Referring to FIG. 2E, a photoresist layer (not shown) is formed to cover part of the oxide layer 34. Then the oxide layer 34, 32, 26 are etched according to the photoresist layer to form a contact window 36 which exposes the drain region 24a. Then, the photoresist layer is removed. The drain region 24a is implanted to form a heavily doped region. Because of the deep node 40 and the shadow effect of the ion implanting process, the node junction 39 can not fully surround the node 40. Therefore, a junction leakage occurs at the outer node junction 41 as shown in FIG. 2E.
Then, a thermal process, for example, a rapid thermal process (RTP), is performed to activate the implanted ions. Necessarily, a native oxide layer will be formed on the surface of the node 40. The native oxide layer will raise the contact resistance of the node 40 and result in difficulty in operating a memory cell.
Referring to FIG. 2F, a polysilicon layer 38 is deposited on the oxide layer 34 and fills in the contact window 36 to make contact with the exposed drain region 24a, wherein the thickness of the polysilicon layer 38 should be enough to provide the needed capacitance. As described above, the native oxide layer is formed on the surface of the node 40 and causes difficulty in operating the memory cell.
Referring to FIG. 2G, the polysilicon layer 38 is defined by conventional lithography technology as shown in FIG. 2G, wherein the polysilicon layer 38 is a lower electrode of a capacitor.
Referring to FIG. 2H, a dielectric layer 46 is formed on the lower electrode 38, wherein the lower electrode 38 is an oxide/nitride/oxide (O/N/O) layer. Then, an upper electrode 48 is formed over the dielectric layer 46.
The conventional finishing process is performed to complete the fabrication of a DRAM capacitor and the finishing process is not described here.
To sum up, the conventional fabricating method of a DRAM capacitor includes at least the following defects:
(1) Because of the deep node and the shadow effect of the ion implanting process, the node junction cannot fully surround the node and thus induces junction leakage. PA1 (2) In forming the polysilicon layer of the lower electrode, a native oxide layer will necessarily be formed on the surface of the substrate and rise the contact resistance to result in operational difficulties for the memory cell.